In fuzzy logic systems there is a need for a circuit to generate a voltage that is either the maximum or the minimum from among a set of N input voltages. Consider first an array of source-follower devices m.sub.1, m.sub.2, . . . and m.sub.N to perform an approximate maximize operation, on a set of input voltages V.sub.1, V.sub.2, . . . and V.sub.N as shown in FIG. 1. An output voltage V.sub.0 will be approximately the maximum of the set of the N input voltages V.sub.1 through V.sub.N, minus a threshold voltage, for small values of I.sub.0 and large values of R. Thus, the source terminal of a source-follower device does not follow the gate voltage precisely and the device has a gain of less than one. Therefore, a static output difference or error arises between the input voltage and the output voltage.
Besides the undesirable threshold voltage drop or static voltage error there is another major cause of non-ideal behavior in the circuit of FIG. 1. When two or more input voltage V.sub.1, V.sub.2, etc. are close together, the current required by the tail source I.sub.0 and load resistor R will flow down through more than one conducting MOS device, i.e. more than one transistor is on at the same time. This means, there will be an erroneous output voltage generated in a transition region when a particular transistor input voltage is gradually assuming its rank as the maximum voltage input level.
To derive a first-order relationship of output voltage to input voltages, from which this error may be clearly seen, consider the case of a somewhat ideal MOS device and its behavior as shown in FIGS. 2A and 2B respectively. Assume the ideal device of FIG. 2A has zero threshold voltage and drain current linearly related to V.sub.GS as shown in FIG. 2B. Specifically, assume I.sub.D =g.sub.m V.sub.GS for V.sub.GS greater than or equal to 0 and I.sub.D =0 for V.sub.GS less than 0. Now, look at a simple case of two input voltages V.sub.1 and V.sub.2 and two corresponding MOS source-followers m.sub.1 and m.sub.2, as shown in FIG. 3. There are three possible regions of operation on the current I.sub.D vs voltage V.sub.GS graph as shown in FIG. 5: transistor m.sub.1 conducting current and transistor m.sub.2 not, transistor m.sub.2 conducting current and transistor m.sub.1 not, and both transistors m.sub.1 and m.sub.2 conducting current.
If transistor m.sub.1 is on and transistor m.sub.2 is off then: EQU V.sub.1 -V.sub.0 &gt;0 and V.sub.2 -V.sub.0 &lt;0; EQU g.sub.m (V.sub.1 -V.sub.0)=I.sub.0 +V.sub.0 /R;
which can be solved to find: EQU V.sub.0 =(V.sub.1 -I.sub.0 /g.sub.m)/(1+1/g.sub.m R),
a function that approximately follows V.sub.1. Similarly if transistor m.sub.2 is on and transistor m.sub.1 is off: EQU V.sub.1 -V.sub.0 &lt;0, V.sub.2 -V.sub.0 &gt;0 and EQU V.sub.0 =(V.sub.2 -I.sub.0 /g.sub.m)/(1+1/g.sub.m R).
Now, the case when both transistors m.sub.1 and m.sub.2 are conducting is governed by V.sub.1 -V.sub.0 .gtoreq.0, V.sub.2 -V.sub.0 .gtoreq.0 and EQU g.sub.m (V.sub.1 -V.sub.0)+g.sub.m (V.sub.2 -V.sub.0)=I.sub.0 +V.sub.0 /R;
solving for V.sub.0 gives V.sub.0 =(V.sub.1 +V.sub.2 -I.sub.0 /g.sub.m)/(2+1/g.sub.m R), and shows an output voltage function that approximately follows the average of V.sub.1 and V.sub.2.
Suppose that V.sub.2 were fixed at some level and V.sub.1 were swept over its maximum range. An ideal maximum-generating circuit would exhibit the characteristic as shown in FIG. 4. In the non-ideal case the two transistor circuit of FIG. 3 would be characterized by the graph shown in FIG. 5.
The width of the transition region(in the center of the graph), when both transistors m.sub.1 and m.sub.2 are conducting drain current, can be found as follows:
When transistor M.sub.1 is on, transistor m.sub.2 will start to conduct when V.sub.0 falls and reaches V.sub.2, so EQU V.sub.0 V.sub.2 =(V.sub.1 -I.sub.0 /g.sub.m)/(1+1/g.sub.m R);
solving for V.sub.1 -V.sub.2 ; EQU V.sub.y =V.sub.1 -V.sub.2 =V.sub.2 /g.sub.m R+I.sub.0 /g.
Similarly when transistor m.sub.2 is on, transistor m.sub.1 will start to conduct when V.sub.0 reaches V.sub.1 as it rises, so EQU V.sub.0 =V.sub.1 =(V.sub.2 -I.sub.0 /g.sub.m)/(1+1/g.sub.m R)
and then solving for V.sub.2 -V.sub.1 gives EQU V.sub.x =V.sub.2 -V.sub.1 =(V.sub.2 /g.sub.m R+I.sub.0 /g.sub.m)/(1+1/g.sub.m R)= V.sub.y /(1+1/g.sub.m R).
From the two plots shown in FIGS. 4 and 5, it can be seen that the actual characteristic will approach the ideal one as g.sub.m approaches infinity. This means that there will be perfect following of the maximum voltage and a zero-width transition region as g.sub.m approaches infinity. It is, of course, impractical to expect a circuit to be designed with unlimited device transconductance, and circuit speed will be severely degraded if single device transconductance is made to be extremely large. This also takes a prohibitive amount of die area.
In addition, as described above a circuit is needed which will not exhibit an output voltage that is actually one threshold voltage lower than the maximum input level, as this simple source-follower circuit would, with real MOS devices.
It is therefore an object of the present invention to provide a provide a circuit which can determine the maximum or minimum of a plurality of analog input voltages which can correct for any D.C. offset error between the output voltage and the maximum or minimum input voltage.
It is yet another object of the present invention to provide a circuit which can determine the maximum or minium of a plurality of analog input voltages which circuit can distinguish between input voltages only a few millivolts apart.
It is a further object of the present invention to provide circuits which can determine the maximum or minimum of a plurality of analog input voltages for single-ended input voltages and a separate circuit for determining the maximum or minimum of a plurality of analolog input voltages for fully-differential input voltages.
Other objects of the invention will become apparent to those of ordinary skill in the art having reference to the following specification, in conjunction with the drawings.